Through - Silicon Via ( TSV ) - induced Noise Characterization and Noise Mitigation using

Through-Silicon Via (TSV) is a critical interconnect element in 3D integration technology. TSVs introduce many new design challenges. In addition to competing with devices for real estate, TSVs can act as a major noise source throughout the substrate. We present in this paper a comprehensive study of TSV-induced noise as a function of several critical design and process parameters including substrate type, signal slew rate, TSV height, ILD thickness, and TSV-to-device and TSV-to-TSV spacing. We create a SPICE model for simulating TSV-to-device and TSV-to-TSV noise couplings in two different types of substrates: a lightly doped bulk substrate, and a lightly doped thin epitaxial layer on top of a heavily doped bulk. Our SPICE model provides small error when compared with a detailed Finite Element Analysis Method. Our findings show the importance of using a grounded backplane in reducing noise and how coaxial TSVs further mitigate TSV-induced noise.